soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的，含蓄的

牛津词典

adj.

• 软性色情的；（性描写等）隐晦的，含蓄的
  showing or describing sexual activity without being too detailed or shocking

柯林斯词典

• (性描写)非赤裸裸的，较隐晦的
  Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

双语例句

• This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU.
  提出了一种基于FPGA（现场可编程门阵列）和软核CPU的嵌入式系统设计的新方法。
• The paper built a soft core processor which named NIOS II in the FPGA by using SOPC technology, and running μ C/ OS-ⅱ operating system on the NIOS II soft-core in order to achieve the scheduling of the system task.
  通过使用SOPC技术，在FPGA内部构建了NIOSⅡ软核处理器，并在NIOSⅡ软核上运行μC/OS-Ⅱ操作系统，从而实现了对系统任务的调度。
• The paper introduces the structural features of the network processor Nios II and customized instructions and design methods for forwarding software of the network processor based on the Nios II soft-core processor and design methods for the DSP processor used for the processing of the video and image data.
  文中介绍了网络处理器NIOSii的结构特点和自定义指令以及基于NIOSii软核处理器的网络处理器转发软件的设计方法和基于视频图像处理的DSP处理器的设计方法。
• This paper introduces 8B/ 10B encoding technique, and puts forward a simple and practical realization method of an 8B/ 10B encoder. Furthermore, a versatile soft-core designed with Verilog is presented.
  本文介绍了8B/10B编码技术，提出了一种简单、实用的8B/10B编码器的实现方法，并且采用Verilog语言设计了一种通用的软核。
• Research and Design of Nios ⅱ Soft-core Processor
  NiosⅡ软核处理器的研究与设计
• First, use of the system functions on a single chip design ideas, using a high-performance soft-core processor ( Nios II CPU) and IP multiplexing and improve the whole system to further improve the speed and flexibility.
  第一，运用了在单芯片上实现系统功能的设计思想，采用了高性能的软核处理器（NiosIICPU）和IP复用技术，提高了整个系统的运行速度和进一步改进的灵活性。
• Nios II soft-core processor implanted into FPGA as the control chip controls and preprocesses the data of the entire image acquisition system.
  采用FPGA作为控制芯片，在其中植入NiosⅡ软核处理器以对整个图像采集系统的数据进行控制和预处理。
• According to the structure model of data acquisition and processing system connected by Ethernet, the network interface module based on the Nios soft-core system is designed to construct the network data acquisition system.
  为构建网络化的数据采集系统，根据数据采集模块与处理控制模块通过以太网相连接的结构模型，设计了基于Nios软核系统的嵌入式以太网网络接口模块。
• Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
  详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。
• First some algorithms of gray-scale quantifying are analysised and simulated, and then the detailed designs of complex mold sub-module, quantifying sub-module and SDRAM soft-core controller is presented. 4.
  先对灰度量化算法进行了分析和仿真比较，然后详细介绍了复数求模子模块、量化子模块、SDRAM控制器的设计。