soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的，含蓄的

牛津词典

adj.

• 软性色情的；（性描写等）隐晦的，含蓄的
  showing or describing sexual activity without being too detailed or shocking

柯林斯词典

• (性描写)非赤裸裸的，较隐晦的
  Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

双语例句

• NIOS ⅱ soft-core processor is a flexible and efficient embedded processor promoted by Altera Corporation.
  NIOSⅡ软核处理器是Altera公司推出的一款灵活高效的嵌入式处理器。
• For the digital part, this design is mean to construct the SOPC system in the FPGA, embedded Nios II soft-core processor to control the operation of the entire system.
  对于数字部分，在FPGA内构建SOPC系统，嵌入NIOSii软核处理器对整个系统进行控制。
• I distinctly remember my high school self, wide-eyed, poring over the soft-core Starr report with friends.
  我还清楚地记得高中时代的我，睁大了眼睛，和朋友们一起狼吞虎咽地读着《斯塔尔报告》（StarrReport）中那些香艳的内容。
• It inherits the hardcore, soft-core, DSP, memory, peripheral I/ O and programmable logic.
  它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。
• With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
  通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。
• The paper introduces the structural features of the network processor Nios II and customized instructions and design methods for forwarding software of the network processor based on the Nios II soft-core processor and design methods for the DSP processor used for the processing of the video and image data.
  文中介绍了网络处理器NIOSii的结构特点和自定义指令以及基于NIOSii软核处理器的网络处理器转发软件的设计方法和基于视频图像处理的DSP处理器的设计方法。
• This paper introduces 8B/ 10B encoding technique, and puts forward a simple and practical realization method of an 8B/ 10B encoder. Furthermore, a versatile soft-core designed with Verilog is presented.
  本文介绍了8B/10B编码技术，提出了一种简单、实用的8B/10B编码器的实现方法，并且采用Verilog语言设计了一种通用的软核。
• In practice, the designer can use this soft-core as a communication module through the FPGA implementation or to quickly build a Field Bus communication system to realize flexible CAN bus interface solutions.
  在实际应用中设计者可以将此软核作为通讯模块通过FPGA实现，或者快速搭建现场总线通信系统，实现灵活的CAN总线接口方案。
• Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
  详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。
• This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU.
  提出了一种基于FPGA（现场可编程门阵列）和软核CPU的嵌入式系统设计的新方法。